1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure of a semiconductor device incorporating an IGBT (Insulated Gate Bipolar Transistor). More particularly, the present invention relates to a structure for reducing an occupation area of a semiconductor device containing a P-channel MOS transistor (insulated gate field effect transistor) provided for improving turn-off characteristics of the IGBT while maintaining breakdown voltage characteristics of the semiconductor device.
2. Description of the Background Art
The IGBT (Insulated Gate Bipolar Transistor) has been known as a power device handling a large electric power. The IGBT contains an MOS transistor (insulated gate field effect transistor) to control the base current of the bipolar transistor, in view of an equivalent circuit. The IGBT has both of an advantage of fast switching characteristics of the MOS transistor and an advantage of high-voltage/large-current processing capacity of the bipolar transistor.
In the IGBT, a low on-voltage and a low switching loss are required for reducing a power loss. Generally, in turn-on of the IGBT, holes of minority carriers are injected from a P-type collector layer into an N-type base layer (drift layer), and a conductivity modulation of an N-drift layer is caused to lower a resistance of the drift layer. When the N-type base layer (drift layer) has the resistance lowered through the conductivity modulation, more electrons are injected from an emitter layer and the IGBT rapidly transits into the on state (conductive state).
In the on state, a collector-to-emitter voltage (on-voltage) is substantially applied across this N-type base layer. In order to reduce this on-voltage, a majority carrier current in the drift layer is increased to decrease the resistance value of the drift layer. In turn-off, however, excessive carriers in the drift layer must be entirely discharged externally from the IGBT or must be annihilated through recombination of electrons and holes. Therefore, when a large amount of excessive carriers are present, a current continues to flow until the carriers are discharged, resulting in increased turn-off loss.
Patent documents 1 and 2 (Japanese Patent Laying-Open Nos. 2003-158269 and 2005-109394) disclose structures for reducing the turn-off loss of the IGBT to rapidly turn off it.
In Patent document 1 (Japanese Patent Laying-Open No. 2003-158269), an insulated gate type control electrode is provided at a surface of a drift layer of an IGBT. In turn-off of the IGBT, a potential of this insulated gate type control electrode is adjusted to absorb holes produced in the drift layer, for suppressing occurrence of a tail current in the turn-off.
In the insulated gate type control electrode disclosed in Patent document 1, the gate insulating film has a thickness, e.g., of 5 nm to 30 nm and the holes are forcedly extracted out through a tunneling phenomenon or an avalanche phenomenon.
In the structure disclosed in Patent document 2 (Japanese Patent Laying-Open No. 2005-109394), a P-channel MOS transistor (insulated gate field effect transistor) is arranged between a collector electrode node and a base of a bipolar transistor. An N-channel MOS transistor for controlling a base current of the bipolar transistor is arranged in series with the P-channel MOS transistor.
The P-channel MOS transistor is kept non-conductive during the operation (on state) of the IGBT, and is set conductive in turn-off to bypass a hole current flowing into the bipolar transistor from the collector electrode. The holes are prevented from being injected into the base layer from the collector electrode in the turn-off, and residual carriers (holes) are rapidly discharged from the drift layer (base layer) of the bipolar transistor, to reduce the switching loss. Thus, the low switching loss and the fast operation in the turn-off may be achieved, while maintaining the low on-voltage of the IGBT.
In the structure disclosed in Patent document 2, the gate insulating film of the P-channel MOS transistor has a thickness that ensures a gate withstanding voltage equal to or larger than, e.g., an element withstanding voltage of the field insulating film or the like, in order to ensure the withstanding voltage during the off state.
In Patent document 1 as described above, the insulated gate control electrode arranged at the surface of the drift layer (base layer) is used for discharging the holes in the turn-off, utilizing the tunneling phenomenon or the avalanche phenomenon. In this case, a high voltage is applied across the insulating film of 5 nm to 30 nm in thickness located under the control electrode, and such a problem may be caused that the breakdown characteristics of this insulating film are liable to deteriorate.
In the structure disclosed in Patent document 1, the insulated gate type control electrode is arranged independently of the control electrode (the gate of the MOS transistor) controlling the turn-on and turn-off of the IGBT. Thus, such a problem may be caused that adjustment between the timing of the turn-on/turn-off of the IGBT and the timing of the voltage application to the insulated gate control electrode may become difficult.
In the structure disclosed in Patent document 2 as described above, the gate electrode of the P-channel MOS transistor is fixed to the ground level, or the gate voltages of both the P- and N-channel MOS transistors are controlled according to the output signal of a common same control circuit.
While the IGBT is off (non-conductive), the P-channel MOS transistor is kept on (conductive). In this state, the gate electrode of the P-channel MOS transistor is supplied with a voltage similar in level to a voltage on the emitter electrode. Therefore, when the P-channel MOS transistor turns on, the gate thereof receives a high voltage similar in level to a collector to emitter voltage Vce. Therefore, for the gate insulating film, the P-channel MOS transistor has a thick insulating film of a thickness larger than or equal to, e.g., a thickness of the field insulating film, for ensuring the withstanding voltage. Consequently, this P-channel MOS transistor has a larger height than N-channel MOS transistors at a periphery thereof, resulting in a problem that a large step or difference in level occurs in the IGBT. Since the P-channel MOS transistor receives the high voltage, a sufficient distance must be kept from the surrounding impurity regions for ensuring the insulation with respect to the impurity regions, which results in undesired increase of the occupation area of the device.